====== Digital Osc. ======
//Digital oscilloscope implemented in a FPGA.//

===== Changelog =====
**Status: ** //Done.//

^ Date ^ Comment ^
| 2006-10-30 | Project created. |

===== About =====
A digital oscilloscope implemented in a FPGA. A signal is sampled via the Audio CODEC and it's waveform is displayed on a CRT/LCD using the vga DAC on an Altera DE2 board (http://www.altera.com/education/univ/materials/boards/unv-de2-board.html).
This project was a part of the Industrial digital contruction course at Chalmers and has been developed by Johan Böhlin, Martin Johansson, Jonatan Åkerlind and Anders Palmér.

===== Hardware =====
The DE2 audio ADC samples the unkown signal at 96kHz. A VHDL block read the sampled value when a certain trigger level occures and store the sampled value to memory. The trigger level, trigger edge and number of samples can be set by the user. A soft processor, NIOS2, read the samples, format it as a wave, adds user interface menus and create a framebuffer. The framebuffer is read by the vga-block which uses the onboard vga DAC to transform the framebuffer to a image on the CRT/LCD. 

{{:hardware:de2.jpg?320 |The altera DE2 board.}} The altera DE2 board.


===== Schematics =====
{{:hardware:idk_block.jpg?320 |Block layout.}} Block layout.

===== Firmware =====
All hardware in VHDL. C for soft CPU. 

===== Downloads =====
A lot of sourcecode. Ask if interested.
The report can be downloaded {{:hardware:idk_report.pdf| here}}.

===== License =====
All information found on this page are licensed. See the [[documents:license]] page for more information.